A conventional high-frequency receiver is described below with reference to drawings.
FIG. 17 is a circuit block diagram of conventional high-frequency receiver 1. In FIG. 17, conventional high-frequency receiver 1 includes input terminal 3 connected to an antenna, electronic tuner 5 for selecting a desired channel from received signals input from this input terminal 3, and demodulator 7 for demodulating I and Q signals output from this electronic tuner 5.
This electronic tuner 5 includes filter 13 passing the received signals from input terminal 3, amplifier 15 receiving an output of this filter 13, mixers 17 and 25 receiving an output of this amplifier through their one inputs, oscillator 33 connected to the other inputs of mixers 17 and 25 via phase shifter 35, compositors 19 and 27 receiving outputs of these mixers 17 and 25 through their one inputs, low-pass filters 21 and 29 receiving outputs of these compositors 19 and 27, respectively; amplifiers 23 and 31 receiving outputs of these low-pass filters 21 and 29, respectively; output terminals 9 and 11 receiving outputs of these amplifiers 23 and 31; DC offset detecting circuit 45 for detecting DC offset voltage, DC offset correcting circuit 47 connected to an output of this DC offset detecting circuit 45 for correcting the DC offset voltage, and DC offset evaluation circuit 46 connected between DC offset detecting circuit 45 and DC offset correcting circuit 47 for evaluating the DC offset voltage.
The first and second cancel signals output from DC offset correcting circuit 47 are supplied to the other inputs of compositors 19 and 27, respectively.
Demodulator 7 includes AD converters 37 and 39 connected to output terminals 9 and 11, respectively; demodulating circuit 41 connected to outputs of these AD converters 37 and 39, respectively; and output terminal 43 receiving a demodulated signal from this demodulating circuit 41. Outputs of A/D converters 37 and 39 are input to offset detecting circuit 45, respectively.
The operation of high-frequency receiver 1 as configured above is described below. Mixing circuit 49 is a direct conversion type mixing circuit including mixers 17 and 25, oscillator 30, and 90-degree phase shifter 35. In this mixing circuit 49, mixers 17 and 25 output I and Q signals with 90° different phases to each other.
These I and Q signals are output from output terminals 9 and 11, via low-pass filters 21 and 29, respectively. In addition, these I and Q signals are converted to digital signals by A/D converters 37 and 39. Then, demodulating circuit 41 converts these signals to demodulated signals and they are output from output terminal 43.
In mixing circuit 49 adopting the direct conversion system as described above, the first and second DC offset voltages are generated in mixers 17 and 25. These first and second DC offset voltages generate DC voltage in received signals, degrading the reception quality.
To reduce this DC offset voltage, the DC offset voltage needs to be corrected. For this purpose, the outputs of A/D converters 37 and 39 are input to DC offset detecting circuit 45, and this offset detecting circuit 45 detects and evaluates the DC offset voltage.
Based on an evaluation result, DC offset correcting circuit 47 outputs first and second cancel signals for canceling out the first and second DC offset voltages, and these cancel signals are input to compositors 19 and 27 to cancel out the first and second DC offset voltage. Patent Literature 1 is one prior art related to the present invention.
Low power consumption is particularly given importance in high-frequency receivers employed in battery-driven devices, such as mobile televisions. However, the conventional high-frequency receiver corrects the DC offset voltage in the state continuously supplying power to DC offset correcting circuit 47. This results in large power consumption.    Patent Literature 1: Japanese Patent Unexamined Publication No. 2003-134183